In recent years, with a trend toward a higher density and a higher degree of integration of a semiconductor integrated circuit (LSI) used for electronic equipment, the number of pins of electrode terminals of a LSI chip has increased and the pitch thereof has decreased rapidly. For mounting these LSI chips on wiring boards, flip chip mounting is used widely in order to decrease a wiring delay. In this flip chip mounting, solder bumps generally are formed on electrode terminals of the LSI chip, which then are joined to connection terminals formed on the wiring board via these solder bumps at one time.
However, in order to mount a next-generation LSI having more than 5,000 electrode terminals on a wiring board, it is necessary to form bumps that correspond to a narrow pitch of 100 μm or less, but it is difficult to adapt to it with a current technique for forming solder bumps. Moreover, since it is necessary to form a large number of bumps that correspond to the number of the electrode terminals, the productivity has to be raised by shortening a mounting tact (mounting time) for each chip, in order to achieve a cost reduction.
Similarly, in the semiconductor integrated circuit, the increase in the number of the electrode terminals has brought about a transition from peripheral electrode terminals to area-disposed electrode terminals. Moreover, due to the demands for a higher density and a higher degree of integration, a semiconductor process is expected to develop from 90 nm to 65 nm and further to 45 nm. As a result, the wiring becomes even finer, and a capacity between the wirings increases, so that problems of speed increase and power consumption loss have become serious. Accordingly, the demand for lowering a dielectric constant (Low-K) of an insulator film between wiring layers has grown further. Since such Low-K of the insulator film is achieved by making an insulator layer material porous, the mechanical strength thereof is low, which obstructs a thickness reduction of the semiconductor. In addition, when structuring the area-disposed electrode terminals as described above, the Low-K raises a problem in the strength of the porous film, making it difficult to form the bumps on the area-disposed electrodes and achieve the flip chip mounting itself Thus, there is a demand for a low-load flip chip mounting method that is adaptable to the future development of the semiconductor process and suitable for a thinner and higher-density semiconductor.
Conventionally, as a technique for forming bumps, plating, screen printing and the like have been developed. The plating is suitable for a narrow pitch, but has a problem in productivity due to its complicated processes. On the other hand, the screen printing has excellent productivity, but is not suitable for narrowing a pitch because of the use of a mask.
In the light of the problems described above, several techniques for forming solder bumps selectively on electrodes of a LSI chip or a wiring board have been developed recently. These techniques not only are suitable for forming fine bumps but also have excellent productivity because they can form the bumps all at one time, which attract attention as techniques that are adaptable to the mounting of the next-generation LSI on the wiring board.
One of these techniques is called a solder paste method (see Patent document 1, for example). In this technique, a solder paste, which is a mixture of electrically conductive particles and flux, is applied solidly onto a substrate whose surface is provided with electrodes, and the substrate is heated so as to melt the electrically conductive particles, whereby solder bumps are formed selectively on the electrodes with high wettability.
Moreover, in a technique called a super solder method (see Patent document 2, for example), a paste-like composition (chemical reaction deposition-type solder) that contains an organic acid lead salt and metal tin as main components is applied solidly onto a substrate on which electrodes are formed, and the substrate is heated so as to cause a substitution reaction between Pb and Sn, thereby depositing a Pb/Sn alloy selectively on the electrodes of the substrate.
However, in both of the solder paste method and the super solder method, since the paste-like composition is supplied onto the substrate by application, local variations in thickness and concentration occur, resulting in variations in the solder deposition amount for individual electrodes. Consequently it is not possible to achieve bumps with uniform heights. Also, in these method, since the paste-like composition is supplied by application onto the wiring board whose surface is provided with the electrodes, namely, with projections or depressions, a sufficient amount Of solder cannot be supplied onto the electrodes serving as the projections, making it difficult to achieve a desired bump height necessary for the flip chip mounting.
By the way, the flip chip mounting using a conventional bump formation technique further requires a process of injecting a resin called an underfill between the semiconductor chip and the wiring board in order to fix the semiconductor chip on the wiring board, after mounting the semiconductor chip on the wiring board on which bumps are formed.
Then, as a method for establishing an electric connection between opposed electrode terminals of the semiconductor chip and the wiring board and fixing the semiconductor chip to the wiring board both at the same time, a flip chip mounting technique using an anisotropic electrically conductive material (for example, see Patent document 3) has been developed. In this technique, by supplying a thermosetting resin containing electrically conductive particles between the wiring board and the semiconductor chip, and then heating the thermosetting resin while applying pressure to the semiconductor chip at the same time, it is possible to establish the electric connection between the electrode terminals of the semiconductor chip and the wiring board and fix the semiconductor chip to the wiring board at the same time. The conventional bump formation is not needed particularly.
The above-described flip chip mounting using the anisotropic conductive material can be considered to have an excellent productivity because the electric connection and the physical fixing between the semiconductor chip and the wiring board can be achieved at the same time without requiring any bump formation. However; since the electric conduction between the electrodes is achieved by mechanical contact via the electrically conductive particles, it is difficult to achieve a stable conductive state.
Moreover, since the electrically conductive particles interposed between the opposed electrodes are maintained by cohesion due to thermal setting of the resin, the properties of the thermosetting resin such as an elastic modulus and a coefficient of thermal expansion and the properties of the electrically conductive particles such as a particle size distribution have to be regulated, leading to a problem of process control being difficult.
In other words, the flip chip mounting using the anisotropic electrically conductive material has many problems to be solved in terms of reliability if it is to be applied to the next-generation LSI chips with more than 5,000 connection terminals.    Patent document 1: JP 2000-94179 A    Patent document 2: JP 1(1989)-157796 A    Patent document 3: JP 2000-332055 A